On the hierarchical design of VLSI processor arrays

The author investigates systematic methods for the design of processor arrays. The proposed concept enables the efficient realization of more general classes of algorithms than the systolic concept. In particular, instance-dependent branching, instance-dependent processor configurations, and hierarchical formulations of imperative programs can be taken into account. The concept of a piecewise-regular dependence graph and that of its reduced description is given. The definition of piece-wise regular algorithms leads to their mapping onto piecewise regular systolic arrays using piecewise linear transformations. The hierarchical description of algorithms and dependence graphs and the corresponding transformations such as condensation, unfolding, clustering and unclustering are applied to partitioning problems (assignment, schedule segmentation, multidimensional mapping)