Title :
A pixel-level ADC with improved performance trade-off for high-speed CMOS imagers
Author :
Boonsobhak, V. ; Worapishe, A.
Author_Institution :
Dept. of Electron. Eng., Mahanakom Univ. of Technol., Bangkok, Thailand
Abstract :
In this paper, an improved circuit configuration of the Nyquist-rate multichannel bit-serial (MCBS) analog-to-digital converter (ADC) for pixel-level CMOS imagers is presented. In this ADC, the folded-cascode and regenerative amplifier topologies are combined to enhance speed and accuracy. The converter comprises a total of 38 transistors and is shared among eight pixels in a time-multiplex manner to allow sufficient accommodation of the circuit and at the same time obtain better accuracy performance from the use of larger transistor sizes. The layout occupies 20×10 μm2 pixel size at 28% fill factor in a 0.35 μm digital CMOS technology. Simulations suggest that speed enhancement by a factor of two and accuracy improvement by more than 2 LSB are feasible.
Keywords :
CMOS image sensors; amplifiers; analogue-digital conversion; circuit simulation; integrated circuit design; integrated circuit modelling; network topology; 0.35 micron; 10 micron; 20 micron; Nyquist-rate multichannel bit-serial analog-to-digital converter; circuit accuracy; circuit configuration; circuit layout; circuit performance; converter transistors; digital CMOS technology; fill factor; folded-cascode amplifier topology; high-speed CMOS imagers; performance trade-off; pixel size; pixel-level ADC; regenerative amplifier topology; simulations; speed enhancement; time-multiplexed converter; transistor sizes; Analog-digital conversion; CMOS digital integrated circuits; CMOS image sensors; CMOS technology; Circuit simulation; Image converters; Microelectronics; Pixel; Quantization; Reflective binary codes;
Conference_Titel :
Circuits and Systems, 2002. APCCAS '02. 2002 Asia-Pacific Conference on
Print_ISBN :
0-7803-7690-0
DOI :
10.1109/APCCAS.2002.1115072
