Dispatching of lots to dynamically reduce the wafers at risk in semiconductor manufacturing

This paper presents a lot dispatching strategy to reduce the Wafer at Risk (W@R) on process tools, i.e. the number of wafers processed between two defectivity inspections. Due to the highly complex manufacturing process and the molecular scope of operations, defectivity inspections are critical for sustaining high yield levels of products. The novel dispatching strategy guides operators in selecting lots that will later be controlled in defectivity. Results show that the system is effective since the impact of measures has improved and the Wafer at Risk on process tools has been reduced.