Title :
Stereo Vision embedded system for Augmented Reality
Author :
Gudis, Eduardo ; Van der Wal, Gooitzen ; Kuthirummal, Sujit ; Chai, Sek ; Samarasekera, Supun ; Kumar, Rakesh ; Branzoi, Vlad
Abstract :
Stereo Vision processing is a critical component of Augmented Reality systems that rely on the precise depth map of a scene to properly place computer generated objects with real life video. Important aspects of the stereo processing are the creation of a dense depth map, high boundary precision, low latency and low power. We present an embedded system for Stereo Vision Processing based on a custom GigE vision board with an Altera Stratix IV FPGA and the Acadia® II System-On-Chip that replaces an existing GPU/PC based system. By porting the stereo algorithm to an FPGA, we reduced the size and power requirements by reducing the workload of the CPU and eliminated the need of a high-end graphics card. The embedded system processes the same algorithm as the GPU/PC based system, but at 10× lower power and lower latency. Placed in a small enclosure, the overall system enables more user mobility for a more compelling user experience.
Keywords :
augmented reality; embedded systems; field programmable gate arrays; stereo image processing; system-on-chip; visual perception; Acadia II system-on-chip; Altera Stratix IV FPGA; CPU workload reduction; GigE vision board; augmented reality; boundary precision; computer generated objects; field programmable gate arrays; graphics card; latency; power requirement reduction; real-life video; scene depth map; size requirement reduction; stereo algorithm; stereo vision embedded system; user mobility; Augmented reality; Cameras; Field programmable gate arrays; Graphics processing unit; Pipelines; Streaming media; System-on-a-chip;
Conference_Titel :
Computer Vision and Pattern Recognition Workshops (CVPRW), 2012 IEEE Computer Society Conference on
Conference_Location :
Providence, RI
Print_ISBN :
978-1-4673-1611-8
Electronic_ISBN :
2160-7508
DOI :
10.1109/CVPRW.2012.6238889