A novel cell arrangement enabling Trench DRAM scaling to 40nm and beyond

Author

Heineck, L. ; Graf, W. ; Popp, M. ; Savignac, D. ; Moll, H.-P. ; Tews, R. ; Temmler, D. ; Kar, G. ; Schmid, J. ; Rouhanian, M. ; Uhlig, I. ; Goldbach, M. ; Landgraf, E. ; Dreeskornfeld, L. ; Drubba, M. ; Lukas, S. ; Weinmann, D. ; Roesner, W. ; Mueller, W

Author_Institution

Qimonda Dresden GmbH & Co. OHG, Munich

fYear

2007

fDate

10-12 Dec. 2007

Firstpage

31

Lastpage

34

Abstract

We present for the first time the full integration scheme and 512 Mb product data for a trench DRAM technology targeting the 48 nm node. The key technology enablers are a new cell architecture "wordline over bitline" (WOB) realizing a high degree of self-alignment and small parasitic capacitances, together with high performance periphery devices at reduced internal voltage, and the integration of a MIC/HfSiO trench capacitor.

Keywords

DRAM chips; hafnium compounds; isolation technology; memory architecture; HfSiO; MIC/HfSiO trench capacitor; cell architecture; cell arrangement; parasitic capacitances; self-alignment degree; size 48 nm; storage capacity 512 Mbit; trench DRAM scaling; trench DRAM technology; wordline over bitline; Capacitors; Conductors; Dielectric devices; Lithography; Low voltage; Microwave integrated circuits; Parasitic capacitance; Random access memory; Technological innovation;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2007. IEDM 2007. IEEE International

Conference_Location

Washington, DC

Print_ISBN

978-1-4244-1507-6

Electronic_ISBN

978-1-4244-1508-3

Type

conf

DOI

10.1109/IEDM.2007.4418855

Filename

4418855