Author :
Kubicek, S. ; Schram, T. ; Paraschiv, V. ; Vos, R. ; Demand, M. ; Adelmann, C. ; Witters, T. ; Nyns, L. ; Ragnarsson, L. Å ; Yu, H. ; Veloso, A. ; Singanamalla, R. ; Kauerauf, T. ; Rohr, E. ; Brus, S. ; Vrancken, C. ; Chang, V.S. ; Mitsuhashi, R. ; Akheya
Abstract :
A gate-first process was used to fabricate CMOS circuits with high performing high-K and metal gate transistors. Symmetric low VT values of plusmn 0.25 V and unstrained IDSAT of 1035/500 muA/mum for nMOS/pMOS at IOFF=100nA/mum and |VDD|=1.1 V are demonstrated on a single wafer. This was achieved using Hf-based high-k dielectrics with La (nMOS) and Al (pMOS) doping, in combination with a laser-only activation anneal to maintain band-edge EWF and minimal EOT re-growth. The laser-only anneal further results in improved LG scaling of 15 nm and a 2 Aring TINV reduction over the spike reference.
Keywords :
CMOS integrated circuits; MOSFET; aluminium; hafnium compounds; high-k dielectric thin films; lanthanum; laser beam annealing; semiconductor doping; tantalum compounds; CMOS circuit fabrication; HfSiO-Al2O3; HfSiON-La2O3; TaC; band-edge EWF; doping; gate-first process; high-K metal gate transistors; laser-only activation annealing; size 15 nm; voltage -2.5 V to 2.5 V; voltage 1.1 V; Annealing; CMOS process; Circuits; Etching; High K dielectric materials; High-K gate dielectrics; Inverters; MOS devices; MOSFETs; Thermal degradation;
