• DocumentCode
    2601804
  • Title

    15 nm Planar Bulk SONOS-type Memory with Double Junction Tunnel Layers using Sub-threshold Slope Control

  • Author

    Ohba, Ryuji ; Mitani, Yuichiro ; Sugiyama, Naoharu ; Fujita, Shinobu

  • Author_Institution
    Toshiba Corp., Yokohama
  • fYear
    2007
  • fDate
    10-12 Dec. 2007
  • Firstpage
    75
  • Lastpage
    78
  • Abstract
    15 nm gate length bulk-planar SONOS-type memory device, which has Si nanocrystal layer lying between double tunnel oxides, retains 2.7 decades memory window for 10 years below 10 V write / erase (w/e) voltages. S-factor is controlled by source/drain (S/D) junction depth and channel concentration. It is experimentally shown that S to D direct tunneling determines a physical limit of S-factor control below 15 nm scale. Further device scaling and improvement by Si nanocrystal scaling are possible within the limit of S-factor control.
  • Keywords
    nanostructured materials; nanotechnology; semiconductor junctions; semiconductor storage; tunnelling; S-factor control; Si nanocrystal scaling; device scaling; direct tunneling; double junction tunnel layers; double tunnel oxide; nanocrystal layer; planar bulk SONOS-type memory; subthreshold slope control; CMOS process; Laboratories; Large scale integration; Nanocrystals; Nonvolatile memory; SONOS devices; Silicon compounds; Temperature; Tunneling; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting, 2007. IEDM 2007. IEEE International
  • Conference_Location
    Washington, DC
  • Print_ISBN
    978-1-4244-1507-6
  • Electronic_ISBN
    978-1-4244-1508-3
  • Type

    conf

  • DOI
    10.1109/IEDM.2007.4418867
  • Filename
    4418867