DocumentCode
2601820
Title
Trap Layer Engineered Gate-All-Around Vertically Stacked Twin Si -Nanowire Nonvolatile Memory
Author
Fu, J. ; Buddharaju, K.D. ; Teo, S.H.G. ; Zhu, Chunxiang ; Yu, M.B. ; Singh, N. ; Lo, G.Q. ; Balasubramanian, N. ; Kwong, D.L.
Author_Institution
Nat. Univ. of Singapore, Singapore
fYear
2007
fDate
10-12 Dec. 2007
Firstpage
79
Lastpage
82
Abstract
Trap layer engineered gate-all-around (GAA) silicon nanowire SONOS memory showing excellent device performance is demonstrated for the first time. Nitride and silicon nanocrystal (Si-NC) has have been incorporated as the engineered charge trapping layer. Fast transient memory characteristic is shown owing to the nanowire channel structure. The device with embedded Si-NC achieves even faster higher memory speed and increased window, up to 3.2 V DeltaVth shift for 1 mus and 6.25 V memory window. The nanowire based non-volatile SONOS memory is promising for the future high speed and low power NAND-type flash memory application.
Keywords
NAND circuits; flash memories; integrated memory circuits; low-power electronics; nanowires; random-access storage; engineered charge trapping layer; fast transient memory characteristic; low power NAND-type flash memory; nonvolatile SONOS memory; nonvolatile memory; silicon nanocrystal; trap layer engineered gate-all-around silicon nanowire; Electrodes; FinFETs; Flash memory; Nanocrystals; Nanoscale devices; Nanostructures; Nonvolatile memory; SONOS devices; Silicon; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 2007. IEDM 2007. IEEE International
Conference_Location
Washington, DC
Print_ISBN
978-1-4244-1507-6
Electronic_ISBN
978-1-4244-1508-3
Type
conf
DOI
10.1109/IEDM.2007.4418868
Filename
4418868
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