Emitter Avalanche Stress on Gated Transistors

Emitter avalanche stress is of growing importance for the study of dielectric coatings on semiconductors and for the investigation of the reliability of devices. In particular certain similarities between the behaviour during high temperature reverse bias testing and B-B avalanching indicate that a study of the failure modes occurring during E-B avalanche stress can provide information on the phenomena occurring during cut-off testing of the same device. This study was done by means of npn transistors with a field plate above the emitter-base junction. The dagradation phenomena occurring during E-B avalanche stress could be described by the generation of recombination centres at the Si-SiO2 interface and by the trapping of negative charge in the oxide. Experimental relationships governing these phenomena were found.