Rail-to-rail input stages: A voltage-mode design technique and a figure-of-merit

The proliferation of battery - operated devices has called for lower supply voltages. Shorter channel lengths and the need for lower supply voltages have made analog design more challenging than ever before. Newer design requirements have also called for a fair comparison metric. This paper evaluates existing CMOS rail-to-rail input stages and introduces a new voltage-mode design technique for CMOS rail-to-rail input stages. Moreover, it establishes a figure-of-merit to assess the overall performance of CMOS rail-to-rail input stages, particularly in low voltage applications. This figure-of-merit, accounts for transconductance variations, input common mode range achieved and power consumption.