DocumentCode
2602754
Title
A highly scaled, high performance 45 nm bulk logic CMOS technology with 0.242 μm2 SRAM cell
Author
Cheng, Kuan-Lun ; Wu, C.C. ; Wang, Y.P. ; Lin, D.W. ; Chu, C.M. ; Tarng, Y.Y. ; Lu, S.Y. ; Yang, S.J. ; Hsieh, M.H. ; Liu, C.M. ; Fu, S.P. ; Chen, J.H. ; Lin, C.T. ; Lien, W.Y. ; Huang, H.Y. ; Wang, P.W. ; Lin, H.H. ; Lee, D.Y. ; Huang, M.J. ; Nieh, C.F.
Author_Institution
Taiwan Semicond. Manuf. Co., Hsinchu
fYear
2007
fDate
10-12 Dec. 2007
Firstpage
243
Lastpage
246
Abstract
A highly scaled, high performance 45 nm CMOS technology utilizing extensive immersion lithography to achieve the industry´s highest scaling factor with ELK (k=2.55) BEOL is presented. A record gate density 2.4X higher than that of 65 nm is achieved. Refined strained-CMOS demonstrated 1200/750 μA/μm Idsat at 100 nA/μm Ioff, Vdd=1 V, which has the best Ion-Lg performance reported for bulk CMOS device. The proposed 45 nm technology is not only manufacturing friendly but also has well-controlled leakage and mismatch evidenced by a functional 32 Mb 0.242 μm2 SRAM.
Keywords
CMOS memory circuits; SRAM chips; immersion lithography; nanoelectronics; nanolithography; ELK BEOL; SRAM cell; bulk logic strained-CMOS technology; immersion lithography; scaling factor; size 45 nm; CMOS logic circuits; CMOS technology; Lenses; Lithography; Manufacturing industries; Random access memory; Refining; Research and development; Resists; Semiconductor device manufacture;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 2007. IEDM 2007. IEEE International
Conference_Location
Washington, DC
Print_ISBN
978-1-4244-1507-6
Electronic_ISBN
978-1-4244-1508-3
Type
conf
DOI
10.1109/IEDM.2007.4418913
Filename
4418913
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