Design Considerations for Complementary Nanoelectromechanical Logic Gates

Author

Akarvardar, K. ; Elata, D. ; Parsa, R. ; Wan, G.C. ; Yoo, K. ; Provine, J. ; Peumans, P. ; Howe, R.T. ; Wong, H.-S.P.

Author_Institution

Stanford Univ., Stanford

fYear

2007

fDate

10-12 Dec. 2007

Firstpage

299

Lastpage

302

Abstract

The operation and performance of complementary nanoelectromechanical (CNEM) logic gates are investigated. NEMS structures featuring dimensions 2 to 3 orders of magnitude smaller than the present MEMS relays are considered. Various metals are benchmarked to silicon as the cantilever beam material. We show that the CNEM inverters featuring laterally actuated beams, 10 nm gap and low density materials such as Si or Al can achieve nanosecond pull-in delay and sub-0.1 fJ switching energy at V_DD = 1.5 V while occupying an area as small as 0.03 mum².

Keywords

CMOS logic circuits; aluminium; beams (structures); cantilevers; elemental semiconductors; integrated circuit design; logic design; logic gates; nanoelectronics; silicon; Al; CMOS technology; CNEM inverters; NEMS structures; Si; cantilever beam material; complementary nanoelectromechanical logic gates design; nanosecond pull-in delay; silicon; switching energy; voltage 1.5 V; Delay; Inorganic materials; Inverters; Logic design; Logic gates; Micromechanical devices; Nanoelectromechanical systems; Relays; Silicon; Structural beams;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2007. IEDM 2007. IEEE International

Conference_Location

Washington, DC

Print_ISBN

978-1-4244-1507-6

Electronic_ISBN

978-1-4244-1508-3

Type

conf

DOI

10.1109/IEDM.2007.4418930

Filename

4418930