A configurable and low complexity hard-decision viterbi decoder in VLSI architecture

Convolutional encoding and viterbi algorithm are basic concepts of error correction method. Specifically, viterbi algorithm is one of decoding method for data error correction. This algorithm is used widely in many communication applications. Hence, many researches have been conducted to achieve an efficient implementation of this algorithm. In VLSI area, the design challenges are usually about its power, area consumption, speed, complexity, and configurability. This paper proposed a configurable and low complexity design for hard-decision viterbi decoder in VLSI. The design can be configured for any number of traceback by increasing or decreasing the size of traceback parameters. It needs N+2 clock cycles latency to complete the process, which N is the number of traceback. In this research, configuration test have been conducted for N=32 and N=64. The design also has been synthesized in both FPGA Altera and Xilinx as target boards. It gives good synthesis results in operational speed and area consumption.