Optimal Integration and Characteristics of Vertical Array Devices for Ultra-High Density, Bit-Cost Scalable Flash Memory

Author

Fukuzumi, Yoshiaki ; Matsuoka, Yasutaka ; Kito, Masanobu ; Kido, M. ; Sato, Mitsuhisa ; Tanaka, Hiroya ; Nagata, Yuichi ; Iwata, Yoshiyuki ; Aochi, H. ; Nitayama, A.

Author_Institution

TOSHIBA Corp., Yokohama

fYear

2007

fDate

10-12 Dec. 2007

Firstpage

449

Lastpage

452

Abstract

Optimal process integration for array devices of bit-cost scalable (BiCS) flash memory is successfully developed. We adopt SiN-based gate dielectrics for the consistency with the ´gate-first´ process which is unique to BiCS flash technology, and ´macaroni´ body FETs for better controllability over the sub-threshold characteristics of depletion-mode poly-silicon transistors. With these technologies and newly devised 4F² cell array, BiCS flash becomes a promising candidate for future ultra-high density memory.

Keywords

field effect transistors; flash memories; integrated memory circuits; SiN; bit-cost scalable flash memory; cell array; depletion-mode polysilicon transistors; gate dielectrics; macaroni body FET; ultra-high density memory; vertical array device characteristics; Controllability; Costs; Dielectrics; Electrodes; FETs; Flash memory; Information systems; Plugs; Proposals; Silicon compounds;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2007. IEDM 2007. IEEE International

Conference_Location

Washington, DC

Print_ISBN

978-1-4244-1507-6

Electronic_ISBN

978-1-4244-1508-3

Type

conf

DOI

10.1109/IEDM.2007.4418970

Filename

4418970