DocumentCode
2603844
Title
Write Strategies for 2 and 4-bit Multi-Level Phase-Change Memory
Author
Nirschl, T. ; Philipp, J.B. ; Happ, T.D. ; Burr, G.W. ; Rajendran, B. ; Lee, M.H. ; Schrott, A. ; Yang, M. ; Breitwisch, T.M. ; Chen, C.F. ; Joseph, E. ; Lamorey, M. ; Cheek, R. ; Chen, S.-H. ; Zaidi, S. ; Raoux, S. ; Chen, Y.C. ; Zhu, Y. ; Bergmann, R. ;
Author_Institution
IBM T.J. Watson Res. Center, Yorktown Heights
fYear
2007
fDate
10-12 Dec. 2007
Firstpage
461
Lastpage
464
Abstract
We discuss novel multi-level write algorithms for phase change memory which produce highly optimized resistance distributions in a minimum number of program cycles. Using a novel integration scheme, a test array at 4 bits/cell and a 32 kb memory page at 2 bits/cell are experimentally demonstrated.
Keywords
semiconductor storage; 2-bit multilevel phase-change memory; 4-bit multilevel phase-change memory; highly optimized resistance distributions; multilevel write algorithm; word length 2 bit; word length 4 bit; Amorphous materials; CMOS technology; Crystallization; Electrodes; Etching; Lithography; Phase change materials; Phase change memory; Testing; Tin;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 2007. IEDM 2007. IEEE International
Conference_Location
Washington, DC
Print_ISBN
978-1-4244-1507-6
Electronic_ISBN
978-1-4244-1508-3
Type
conf
DOI
10.1109/IEDM.2007.4418973
Filename
4418973
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