DocumentCode
2603851
Title
Influence of buffers on RISC core performance [HDTV source decoder system]
Author
Zhou, L. ; Yao, Q.D. ; Liu, P. ; Li, D.X.
Author_Institution
Dept. of Inf. Sci. & Electron. Eng., Zhejiang Univ., Hangzhou, China
Volume
2
fYear
2002
fDate
2002
Firstpage
283
Abstract
In an HDTV source decoder system, an efficient bus plays an important role in maximizing the system performance. This paper proposes two models to evaluate how the buffer and priority schemes in bus arbitration unit can affect HDTV decoder system performance. A Store Probability and Buffer Size (SP-BS) model and Capability Performance Formula (CPF) model are proposed to investigate the influence of the buffer on system performance, and to obtain a quantitative relation between them. According to the models, an optimal buffer size with the highest performance/cost ratio for benchmarks can be obtained.
Keywords
VLSI; buffer storage; decoding; digital signal processing chips; high definition television; performance evaluation; reduced instruction set computing; video coding; HDTV source decoder system; RISC core performance; buffer influence; bus arbitration unit; capability performance formula model; optimal buffer size; priority schemes; store probability buffer size model; system performance; Application specific integrated circuits; Buffer storage; Clocks; Decoding; HDTV; Information science; Reduced instruction set computing; Switches; System performance; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2002. APCCAS '02. 2002 Asia-Pacific Conference on
Print_ISBN
0-7803-7690-0
Type
conf
DOI
10.1109/APCCAS.2002.1115231
Filename
1115231
Link To Document