Optimal design of a multiplying D/A converter stage with time-shifted correlated double sampling

The multiplying D/A converter stage with time-shifted correlated double sampling technique is analyzed. Comprehensive models for the residual error due to finite amplifier gain and the thermal noise power are derived; the settling behavior of such stages is presented. It is shown that the selection of the error storage/hold capacitance introduces tradeoffs with respect to noise, accuracy, and power consumption. The link between the optimal hold capacitance leading to minimum power and the converter speed is demonstrated.