An Effective Switching Current Methodology to Predict the Performance of Complex Digital Circuits

Author

Von Arnim, Klaus ; Pacha, Christian ; Hofmann, Karl ; Schulz, Thomas ; Schrüfer, Klaus ; Berthold, Jörg

Author_Institution

Infineon Technol., Munich

fYear

2007

fDate

10-12 Dec. 2007

Firstpage

483

Lastpage

486

Abstract

A new methodology to assess dynamic circuit performance using basic device currents is presented. In contrast to existing effective drive current calculation considering inverters only, our approach provides precise circuit delays of product-relevant NAND and NOR logic gates over a wide range of supply voltages. The relevance of currents in the linear regime for circuit performance in sub-65 nm CMOS technologies is demonstrated also experimentally by a 65% performance boost in complex multi-gate FET circuits.

Keywords

CMOS logic circuits; delay circuits; field effect transistor circuits; logic gates; CMOS technologies; NAND logic gate; NOR logic gates; circuit delays; complex digital circuits; multigate FET circuits; size 65 nm; switching current methodology; CMOS logic circuits; CMOS technology; Circuit optimization; Delay effects; Digital circuits; Logic circuits; Logic devices; Logic gates; Pulse inverters; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2007. IEDM 2007. IEEE International

Conference_Location

Washington, DC

Print_ISBN

978-1-4244-1507-6

Electronic_ISBN

978-1-4244-1508-3

Type

conf

DOI

10.1109/IEDM.2007.4418979

Filename

4418979