Improved Vt Stability of SNOS FETs by Oxygen Annealing

The threshold voltage stability of p- and n-channel silicon gate FETs is improved by annealing the gate silicon nitride in oxygen or steam prior to deposition of the silicon gate. Annealing shifts the threshold voltage negatively by 100-200mV, and lowers the normalized transconductance slightly. Field effect mobility, fast surface state density and junction leakage are not affected by the anneal. Formation of a thin layer of SiO2 plus SiOXNy during annealing increases nitride resistivity and reduces the threshold voltage shift due to charge storage at the oxide-nitride interface.