Title :
Gate-First Processed FUSI/HfO2/HfSiOx/Si MOSFETs with EOT=0.5 nm - Interfacial Layer Formation by Cycle-by-Cycle Deposition and Annealing
Author :
Takahashi, M. ; Ogawa, Anna ; Hirano, A. ; Kamimuta, Y. ; Watanabe, Y. ; Iwamoto, K. ; Migita, S. ; Yasuda, N. ; Ota, H. ; Nabatame, T. ; Toriumi, A.
Author_Institution :
AIST Tsukuba West 7, Ibaraki
Abstract :
We have successfully fabricated a 0.5 nm FUSI-NiSi/ HfO2 HfSiOx/ Si gate stack structure with the gate-first process. The HfSiOx interfacial layer was formed by the cycle-by-cycle deposition and annealing process, followed by the in-situ layer-by-layer deposition and annealing for HfO2 growth. The gate leakage current of ~ 10 A/cm at Vfb - 1.0 V and the effective electron mobilityof 120 cm2/Vs at 0.8 MV/cm were obtained for n-MOSFET with EOT = 0.49 nm.
Keywords :
MOSFET; annealing; atomic layer deposition; electron mobility; hafnium compounds; high-k dielectric thin films; leakage currents; nickel compounds; semiconductor device models; semiconductor device reliability; CC-IL formation; EOT; FUSI gate stack structure fabrication; NiSi-HfO2-HfSiOx-Si; annealing process; cycle-by-cycle deposition; effective electron mobility; equivalent oxide thickness; gate leakage current; gate-first process; high-k gate dielectrics; in-situ high-k gate stack process; in-situ layer-by-layer deposition; n-MOSFET; semiconductor interfacial layer; size 0.49 nm; size 0.5 nm; voltage 1.0 V; Annealing; Capacitance; Electrodes; Fabrication; Hafnium oxide; High K dielectric materials; High-K gate dielectrics; Leakage current; MOSFETs; Substrates;
Conference_Titel :
Electron Devices Meeting, 2007. IEDM 2007. IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
978-1-4244-1507-6
Electronic_ISBN :
978-1-4244-1508-3
DOI :
10.1109/IEDM.2007.4418990
