On the use of body biasing to control gain, linearity, and noise figure of a mm-wave CMOS LNA

In this paper, the use of body biasing to control gain, linearity, and noise figure in CMOS low-noise amplifiers (LNAs) is investigated. As a proof of concept, a 60-GHz 4-stage cascode CMOS variable-gain LNA is designed and laid out in a 6 5nm CMOS technology. To improve the accuracy of the post-layout simulations, all inductors are modeled and simulated with a 3-dimentional electromagnetic solver. Post-layout simulation results show that the LNA achieves a maximum gain of 23.5 dB at 60 GHz while consuming 38 mW from a 1.2-V supply. By changing the body bias voltage of the transistors in the two intermediate stages, the overall gain varies from 13 to 23.5 dB providing more than 10 dB of gain range. Adjusting the body biasing of the transistors in the first and last stage, respectively, results in a minimum noise figure of 6.5 dB at 60 G Hz and the maximum IIP3 of more than +1dBm for the overall amplifier.