Practical dual-metal-gate dual-high-k CMOS integration technology for hp 32 nm LSTP utilizing process-friendly TiAlN metal gate

We propose a new dual-metal-gate dual-high-k CMOS integration technology using TaSiN gate HfSiON n-FET and TiAIN gate HfAlSiON p-FET for hp 32 nm low standby power (LSTP) CMOS devices. Low V, of p-FET, namely high effective work function of 4.8 eV was obtained due to spontaneous AIN-cap formation of TiAIN and subsequent intermixing between AIN-cap and HfSiON by high temperature annealing. There was no degradation in gate leakage current and electron mobility in TaSiN gate HfSiON n-FET even if TaSiN was formed after TiAIN removal. Thus, this technique is practical for realizing dual-metal-gate dual-high-k CMOS devices.