Screening of Metallization Step Coverage on Integrated Circuits

Scanning electron microscopy is widely used to screen step coverage of interconnects on planar semiconductor devices. Utilization of this method has produced many sampling plans. This paper presents the results of a SEM examination of regional and slice-to-slice variances of oxide step contours and metal coverage. High-current pulse testing of aluminum stripes crossing oxide steps was also investigated as an electrical alternative to a SEM screen. The results of this study indicate that when slice-to-slice variances in oxide contour can occur, the quality of metallization must be judged on a slice basis and a SEM examination of each type step in a relatively small region adequately characterizes the slice.