Mixed-level modeling in VHDL using the watch-and-react interface

Using VHDL, it is possible to model systems at many different levels of detail. The various modeling levels (performance, behavioral, etc.) can also be intermixed to create mixed-level models. The paper describes the watch-and-react interface which was created to resolve the differences in timing and data abstraction between the performance modeling domain (token based) and the behavioral modeling domain (value based). Specifically this interface is useful for integrating behavioral models of complex sequential components into performance models. It operates by monitoring the “important” signals in a system and then reacting to changes in these signals by generating tokens or forcing signals to appropriate values given the particular situation. The two main elements in the interface are the trigger and the driver. Program files containing scripting instructions are interpreted by the these two elements as the VHDL model simulates