Hardware/software Co-design of NLMS adaptive filters on FPGA

The NLMS adaptive filter is an important component of many DSP systems including acoustic echo cancellers and channel equalizers. In real-time applications, such filters often require dedicated hardware to meet the timing requirements. Modern FPGAs fulfill the above demand for its excellent flexibility and performance. This paper proposes two different architectures for implementing an NLMS adaptive filtering algorithm, using a 32 bit fixed-point arithmetic representation, on FPGA. These architectures are implemented using the Altera Cyclone II FPGA DE2-70 development board. A pure software implementation of the algorithm is first proposed using NIOS II embedded RISC processor. An FIR filter core is then proposed to implement a HW/SW Co-design architecture with the existing embedded processor. A comparison is made between the two alternative architectures for performance and area usage. Results show a significant improvement in execution time required when implementing with HW/SW Co-design over a pure software implementation.