Technology Circuit Co-Design for High Performance Logic

Achieving maximum logic performance at minimum power consumption in deeply scaled CMOS technologies requires the cooperative design of technology, circuits, and architecture. The objective of this paper is to examine the interaction of technology and circuits in highly synchronous logic, and the factors which influence the size of the functionality window and the circuit-limited-yield across process and over time. Specific circuit topology as well as generic chip responses will be explored and tied back to underlying idiosyncrasies of the field effect transistor.