DocumentCode
2604902
Title
Constructive pattern generation heuristic for meeting SSO limits
Author
Baker, Kendrick
Author_Institution
Raytheon Co., McKinney, TX, USA
Volume
2
fYear
2003
fDate
30 Sept.-2 Oct. 2003
Firstpage
50
Abstract
This paper discusses a heuristic for generating a minimal number of true/complement patterns while still meeting simultaneous switching requirements. The algorithm presented herein generates the patterns by construction, as opposed to selecting the patterns from a larger superset of possible patterns. This potentially offers advantages in time and memory, since no information about the superset needs to be stored or analyzed. In addition, the algorithm appears to produce good results, which in this case means small pattern sets while maintaining the same high level of fault coverage offered by other methods.
Keywords
automatic test pattern generation; boundary scan testing; electronic engineering computing; integrated circuit interconnections; SSO limits; constructive pattern generation heuristic; fault coverage; pattern sets; simultaneous switching requirements; true/complement patterns; Bonding; Inductance; Information analysis; Packaging; Parasitic capacitance; Pins; Switches; Testing; Voltage; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 2003. Proceedings. ITC 2003. International
ISSN
1089-3539
Print_ISBN
0-7803-8106-8
Type
conf
DOI
10.1109/TEST.2003.1271194
Filename
1271194
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