Design and implementation of IEEE 1149.6

This paper describes the implementation of 1149.6 to an existing commercial high-speed interface device. The first section explains the circuit design decisions made during the definition phase. The insertion of the test circuitry was carefully implemented to co-exist with the mission mode circuitry. The second section describes the effect of the test circuit on the high-speed mission performance of the device and the trade-offs that those effects imposed. After the implementation phase, the test circuit was simulated, verified, manufactured in silicon and tested. The third part of the paper report the findings after the verification and simulation of the functional performance of the IEEE 1149.6 device. An important consideration for the verification process is to determine the fault coverage of AC-coupled line tests. The specific behavior of the test circuit during detection of various faults directly governs the design of the IEEE 1149.6 TAP (test access port) controller. The end presents a summary and discussion of the results. In addition to the performance of the 1149.6 implementation, a brief comparison between the features and characteristics of the IEEE 1149.4 (mixed signal test bus) and IEEE 1149.6 standard are presented.