DocumentCode
2605008
Title
IBIST™ (interconnect built-in-self-test) architecture and methodology for PCI Express
Author
Nejedlo, Jay J.
Author_Institution
Enterprise Platforms Div., Intel Corp., Hillsboro, OR, USA
Volume
2
fYear
2003
fDate
30 Sept.-2 Oct. 2003
Firstpage
114
Abstract
This paper summarizes the test challenges associated with next generation platform buses and introduces an Intel developed technology called IBIST™ created to meet those challenges. The IBIST™ testing methodology and associated on-die architecture customized for the PCI Express (PCIe) interface are described.
Keywords
built-in self test; integrated circuit interconnections; peripheral interfaces; production testing; IBIST™; Intel; PCI Express interface; interconnect built-in-self-test; on-die architecture; platform buses; testing methodology; Built-in self-test; Circuit testing; Electromagnetic interference; Integrated circuit interconnections; Manufacturing; Power transmission lines; Production facilities; Routing; Silicon; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 2003. Proceedings. ITC 2003. International
ISSN
1089-3539
Print_ISBN
0-7803-8106-8
Type
conf
DOI
10.1109/TEST.2003.1271201
Filename
1271201
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