Three-dimensional Modeling of Gate Leakage in Si Nanowire Transistors

Author

Luisier, Mathieu ; Schenk, Andreas ; Fichtner, Wolfgang

Author_Institution

ETH Zurich, Zurich

fYear

2007

fDate

10-12 Dec. 2007

Firstpage

733

Lastpage

736

Abstract

The gate currents of Si nanowire transistors are investigated using a three-dimensional, real-space, and self-consistent Schrodinger-Poisson solver. The influence of the gate material (metal or poly-Si) and the choice of the dielectric (SiO₂ or high-kappa stacks) are studied in details. Then, the performances of nanometer-scaled triple-gate structures are analyzed with respect to ON- and OFF-currents, subthreshold swing, and threshold voltage.

Keywords

MOSFET; Poisson equation; Schrodinger equation; dielectric materials; elemental semiconductors; leakage currents; nanoelectronics; nanowires; semiconductor device models; silicon; MOSFET; Si; dielectric materials; gate materials; nanometer-scaled triple-gate structures; self-consistent Schrodinger-Poisson solver; silicon nanowire transistors; subthreshold swing; three-dimensional gate current leakage modeling; threshold voltage; Dielectric constant; Effective mass; Electrons; FETs; Gate leakage; Leakage current; MOSFETs; Nanoscale devices; Schrodinger equation; Tin;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2007. IEDM 2007. IEEE International

Conference_Location

Washington, DC

Print_ISBN

978-1-4244-1507-6

Electronic_ISBN

978-1-4244-1508-3

Type

conf

DOI

10.1109/IEDM.2007.4419051

Filename

4419051