1-D and 2-D Devices Performance Comparison Including Parasitic Gate Capacitance and Screening Effect

This paper studies the parasitic capacitance of 1-dimensional (1D) and 2-dimensional (2D) MOSFETs by numerical simulation and analytical models. We show that 1D devices are not necessarily the better choice over 2D devices for future technologies, especially for low channel densities and narrow gate widths. For W_gate<10L_g, the delay improvement is overestimated from the intrinsic case by at least 30%-60% from ignoring parasitics and channel screening effects, for channel density from 400/mum-25/mum. A methodology for 1D device design optimization is proposed, followed by a possible scaling path of 1D devices down to 11 nm node. The analytical model is a first step toward a compact model for 1D FETs.