DocumentCode :
2605290
Title :
1-D and 2-D Devices Performance Comparison Including Parasitic Gate Capacitance and Screening Effect
Author :
Wei, Lan ; Deng, Jie ; Wong, H. S Philip
Author_Institution :
Stanford Univ., Stanford
fYear :
2007
fDate :
10-12 Dec. 2007
Firstpage :
741
Lastpage :
744
Abstract :
This paper studies the parasitic capacitance of 1-dimensional (1D) and 2-dimensional (2D) MOSFETs by numerical simulation and analytical models. We show that 1D devices are not necessarily the better choice over 2D devices for future technologies, especially for low channel densities and narrow gate widths. For Wgate<10Lg, the delay improvement is overestimated from the intrinsic case by at least 30%-60% from ignoring parasitics and channel screening effects, for channel density from 400/mum-25/mum. A methodology for 1D device design optimization is proposed, followed by a possible scaling path of 1D devices down to 11 nm node. The analytical model is a first step toward a compact model for 1D FETs.
Keywords :
MOSFET; optimisation; semiconductor device models; 1D device design optimization; 2-dimensional MOSFET; channel density; parasitic gate capacitance; screening effect; Analytical models; Delay; Electrostatics; Equations; FETs; Geometry; MOSFETs; Nanoscale devices; Parasitic capacitance; Quantum capacitance;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting, 2007. IEDM 2007. IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
978-1-4244-1507-6
Electronic_ISBN :
978-1-4244-1508-3
Type :
conf
DOI :
10.1109/IEDM.2007.4419053
Filename :
4419053
Link To Document :
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