Title :
Reconfigurable execution core for high performance DSP applications
Author :
Rath, A.K. ; Meher, P.K.
Author_Institution :
Kalinga Inst. of Ind. Technol., Bhubaneswar, India
Abstract :
The paper presents an execution core which can be reconfigured either for calculation of digital convolution or for computation of discrete orthogonal transform by appropriate local buffer initialization of processing cells. It is shown that the data flow pattern can be changed by a single bit control signal. The massively parallel proposed execution core will yield high throughput for multimedia and image processing DSP applications.
Keywords :
convolution; digital signal processing chips; discrete transforms; multimedia computing; reconfigurable architectures; data flow pattern; digital convolution; discrete orthogonal transform; high performance DSP applications; image processing DSP; local buffer initialization; multimedia DSP; processing cells; reconfigurable execution core; single bit control signal; throughput; Adaptive filters; Convolution; Digital signal processing; Discrete Fourier transforms; Embedded system; Filter bank; Finite impulse response filter; Fourier transforms; Registers; System-on-a-chip;
Conference_Titel :
Circuits and Systems, 2002. APCCAS '02. 2002 Asia-Pacific Conference on
Print_ISBN :
0-7803-7690-0
DOI :
10.1109/APCCAS.2002.1115323
