• DocumentCode
    2605831
  • Title

    Implementation of base station receiver for CDMA wireless local loop system

  • Author

    Chung, Jae W. ; Kim, Jin S. ; Jeong, Young G. ; Ha, Jeong S.

  • Author_Institution
    Electron. & Telecommun. Res. Inst., Taejon, South Korea
  • fYear
    1997
  • fDate
    17-19 Dec 1997
  • Firstpage
    371
  • Lastpage
    374
  • Abstract
    The wireless local loop (WLL) system has been deployed as a new application for wireless communication with fixed subscriber units which impose a fixed to fixed propagation and no handoffs compared to the wireless mobile communication systems. The design of the WLL system is much simpler than that of a mobile system because no handoff occurs in a fixed-to-fixed link. This paper describes the hardware design and implementation of base station receiver for code division multiple access (CDMA) WLL system proposed by Electronics and Telecommunications Research Institute (ETRI). This base station demodulator module of the WLL system is implemented by hardware chips, such as a digital signal processor (DSP), erasable programmable logic device (EPLD), and a field programmable gate array (FPGA). Timing simulation of the implemented system is operated using the ALTERA MAXPLUS tool. The basic hardware modules of the base station receiver consist of two searchers for antenna diversity and four fingers for multipath combining. We verify the operation of the code acquisition and time tracking loop on the call test. The reconstructed speech shows a good quality in the reverse link
  • Keywords
    code division multiple access; demodulators; digital signal processing chips; digital simulation; diversity reception; field programmable gate arrays; land mobile radio; multipath channels; radio receivers; subscriber loops; timing; ALTERA MAXPLUS tool; CDMA; DSP chips; EPLD; ETRI; Electronics and Telecommunications Research Institute; FPGA; antenna diversity; base station receiver; code acquisition; code division multiple access; demodulator module; digital signal processor; erasable programmable logic device; field programmable gate array; fixed subscriber units; handoffs; hardware design; multipath combining; reconstructed speech quality; reverse link; time tracking loop; timing simulation; wireless local loop system; wireless mobile communication systems; Base stations; Demodulation; Digital signal processors; Diversity reception; Field programmable gate arrays; Hardware; Mobile communication; Multiaccess communication; Programmable logic arrays; Wireless communication;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Personal Wireless Communications, 1997 IEEE International Conference on
  • Conference_Location
    Mumbai
  • Print_ISBN
    0-7803-4298-4
  • Type

    conf

  • DOI
    10.1109/ICPWC.1997.655544
  • Filename
    655544