Building blocks for delay-insensitive circuits using single electron tunneling devices

This paper presents a set of basic building blocks that corresponds to a universal set of primitives for delay insensitive circuits. We propose single electron tunneling circuit topologies and verify them by means of simulations. The simulations performed with SIMON 2.0 indicate that the circuits function as expected. Moreover the proposed circuits are input-output level compatible thus they can be potentially utilized in the implementation of larger asynchronous circuits.