Title :
Design of Generic Floating Point Multiplier and Adder/Subtractor Units
Author :
Hamid, Lamiaa S A ; Shehata, Khaled A. ; El-Ghitani, Hassan ; ElSaid, Mohamed
Author_Institution :
ECE Dept., Misr Int. Univ., Cairo, Egypt
Abstract :
A high speed generic Floating Point Unit (FPU) consisting of a multiplier and adder/subtractor units is proposed. A novel multiplication algorithm is proposed and used in the multiplier implementation. The new algorithm depends on dividing the multiplication operation into several smaller multiplications performed in parallel. The output from these multiplications is then manipulated in a manner to give the final result of the original multiplication operation. The adder/subtractor unit is implemented using the Leading One Detector (LOD) algorithm. In order to achieve high maximum, speed, both units were deeply pipelined. The design is written using VHDL code and mapped to Virtex2, Virtex4 and Virtex5 FPGAs. Both units can operate at more than 400 MHz on Virtex4.
Keywords :
adders; field programmable gate arrays; floating point arithmetic; multiplying circuits; VHDL code; Virtex2 FPGA; Virtex4 FPGA; Virtex5 FPGA; adder/subtractor units; generic floating point multiplier design; generic floating point unit; leading one detector algorithm; multiplication algorithm; multiplication operation; Computational modeling; Computer architecture; Computer simulation; Detectors; Field programmable gate arrays; Floating-point arithmetic; Frequency; Hardware; Neck; Signal processing algorithms; FPGA; Pipelined Architecture; floating point;
Conference_Titel :
Computer Modelling and Simulation (UKSim), 2010 12th International Conference on
Conference_Location :
Cambridge
Print_ISBN :
978-1-4244-6614-6
DOI :
10.1109/UKSIM.2010.117
