Integrated approach for circuit and fault extraction of VLSI circuits

Author

Gonçalves, F.M. ; Teixeira, I.C. ; Teixeira, J.P.

Author_Institution

INESC/IST, Lisbon, Portugal

fYear

1996

fDate

6-8 Nov 1996

Firstpage

96

Lastpage

104

Abstract

The purpose of this paper is to present a methodology for circuit and realistic fault extraction, and its implementation in a new tool, under development. To be included in a virtual test environment, DOTLab. Digital, analog and mixed signal ICs, implemented in CMOS, bipolar or BiCMOS technologies are handled, both in Manhattan and 45° geometries. For complex circuits, higher level information, obtained in the top-down design flow, is used for fault characterization. A sliding window algorithm previously used for circuit extraction, is extended for fault extraction of non-orthogonal geometries

Keywords

BiCMOS integrated circuits; CMOS integrated circuits; VLSI; automatic test software; bipolar integrated circuits; circuit analysis computing; fault diagnosis; integrated circuit layout; integrated circuit testing; 45° geometry; BiCMOS technology; CMOS technology; DOTLab; Manhattan geometry; VLSI circuits; analog ICs; bipolar technology; circuit extraction; digital ICs; fault characterization; fault extraction; higher level information; mixed signal ICs; nonorthogonal geometries; sliding window algorithm; top-down design flow; virtual test environment; CMOS technology; Circuit faults; Circuit testing; Data mining; Geometry; Integrated circuit layout; Integrated circuit noise; Integrated circuit testing; Libraries; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 1996. Proceedings., 1996 IEEE International Symposium on

Conference_Location

Boston, MA

ISSN

1550-5774

Print_ISBN

0-8186-7545-4

Type

conf

DOI

10.1109/DFTVS.1996.572002

Filename

572002