32 nm node Ultralow-k(k=2.1)/Cu Damascene Multilevel Interconnect using High-Porosity (50 %) High-Modulus (9 GPa) Self-Assembled Porous Silica

Feasibility for 32 nm node interconnect is depended on porous dielectric process technology. Self-assembled porous silica as a recent highest porosity material (50%) was successfully introduced into 200 nm pitch low-k/Cu damascene. The key technologies obtained in this work were novel rapid silylation hardening process with low temperature adsorption followed by rapid annealing, and reliable pore management at trench sidewall to introduce highly porous material to the low-k/Cu integration process. Performances of these technologies were confirmed to be extendible to 32 nm node, 100 nm pitch interconnects.