Constant coefficient convolution implemented in FPGAs

This paper reviews different architectural solutions for calculating constant coefficient convolution operation in FPGAs. At first, different architectures of multipliers are approached, as the multiplication is the most complex operation performed in the convolutions. Nevertheless, disregarding the multiplier entity allows for further circuit optimisations. Therefore look-up-table (LUT) based convolver (LC) versus the sum of the LUT-based Multipliers are described. Further, an alternative technique - (Parallel) distributed arithmetic convolver (DAC) is approached. The key issue of this paper is, however, a novel architectural solution: irregular distributed arithmetic convolver (IDAC) which, in comparison to the DAC, has an irregular form, and therefore allows for better circuit optimisation. All architectural solutions described hereby can be automatically generated by the automated tool for generation convolvers in FPGAs (AuToCon).