Gate Protection for CMOS/SOS

Pulse-power burn-out test results on SOS resistors, high voltage diodes, and thermally grown gate oxides are described. For SOS diffused resistors, the failure power per unit area ranged from 4 × 106 to 3.7 × 105 watts/cm2 for pulse widths of 100 nanoseconds to 10 microseconds. The failure mechanism is heat-induced resistivity variation resulting in formation of low resistivity hot spots or filaments. High voltage diode and resistor combinations extended the failure voltages to 325 volts for 100 nanosecond pulses. These protection networks were evaluated for use as on-chip protection of CMOS/SOS IC gate oxides. For these gate oxides, the dielectric strength of ~800Å thick silicon dioxide on SOS was~7 × 106 volts/cm for 100 nanosecond pulses.