FPGA-Accelerated Design of Motion Estimation for H.264 HDTV

H.264/AVC is a merging popular video coding standard which have new features. A H.264 open source, X264 code set, adopt motion estimation which consists of diamond search, hexagonal search, uneven multi-hexagon search, exhaustive search and hadamard exhaustive search. According to statistic values, the time-consuming of ME operations during HDTV(1920x1080p) encoding is about 60-80 percent within whole H.264 algorithm. Considering the characteristics of FPGAs, flexibility, inherent parallel characteristic and the rapid prototyping, a parallel operation architecture of FPGA-based was designed with a Lattice ECP2M chip. The experiment results which include the time-consuming, the wave forms and the calculation cycles were analyzed with special tools, ispLever 6.1, ModelSim, etc. and the Post-Place & Route layout of a project was shown in the end of this paper. It is concluded that the FPGA chip can deal with HDTV sequences as a co-processor in a video coding system.