Plasma doping for S/D extensions: device integration, gate oxide reliability and dynamic behavior

Author

Dumont, Benjamin ; Pouydebasque, Arnaud ; Lallement, Fabrice ; Lenoble, Damien ; Ribes, Guillaume ; Roux, Julien-Marc ; Vanbergue, Sebastien ; Skotnicki, Thomas

Author_Institution

STMicroelectron., Crolles, France

fYear

2005

fDate

12-16 Sept. 2005

Firstpage

113

Lastpage

116

Abstract

We present in this paper electrical results where the ultra low energy (ULE) implantation is replaced by plasma doping (PLAD) process for the source/drain extensions (SDE) for both PMOS and NMOS devices. We show good I_on/I_off performances (730μA/μm/320μA/μm at Ioff -100nA/μm) on isolated transistors especially with a gain for NMOS devices and we discuss on the improvement of several "secondary" parameters like SDE resistance or junction leakage. Secondly, gate oxide reliability electrical tests show that PLAD does not damage gate oxide integrity. Finally we demonstrate the improvement of dynamic performance using PLAD through RO measurement.

Keywords

MOSFET; nanoelectronics; semiconductor device reliability; semiconductor doping; NMOS devices; PMOS devices; SDE resistance; device integration; gate oxide reliability; isolated transistors; junction leakage; plasma doping process; ultra low energy implantation; Annealing; Doping; Integrated circuit reliability; MOS devices; Performance gain; Plasma devices; Plasma sources; Ring oscillators; Semiconductor device reliability; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Device Research Conference, 2005. ESSDERC 2005. Proceedings of 35th European

Print_ISBN

0-7803-9203-5

Type

conf

DOI

10.1109/ESSDER.2005.1546598

Filename

1546598