A preprocessing architecture for resolution enhancement in high speed analog-to-digital converters

High performance analog-to-digital converters (ADCs) employ a parallel configuration of analog folding circuits to symmetrically fold the input signal prior to quantization by high speed comparators (analog preprocessing). A new preprocessing approach is identified. It can be easily incorporated into the established techniques to provide an enhanced resolution capability. The approach is based on preprocessing the analog signal with a symmetrical number system (SNS). The SNS preprocessing is used to decompose the analog amplitude analyzer operation into a number of suboperations (moduli) which are of smaller computational complexity. Each suboperation symmetrically folds the analog signal with folding period equal to the moduli. A much higher resolution is achieved after the N different SNS moduli are used, and the results of these low precision sub-operations are recombined. The SNS framework can extend the resolution capabilities of these ADC architectures without a loss in high-speed performance. Circuit designs and simulations are demonstrated to verify the performance of the SNS concept