The Application of Electrical Overstress Models to Gate Protective Networks

The study of electrical overstress failure in bipolar semiconductor devices from transients induced from nuclear electromagnetic pulses has resulted in: (1) understanding of failure mechanisms, (2) models to predict failure levels, (3) test techniques, and (4) guidance for hardness assurance and reliability of gate input protective networks. The applicability of failure mechanisms and models for components of gate input protective networks such as resistors, diodes, and interconnect metallization stripes is shown. References to representative detailed publications are given.