Enhancement of data retention time in DRAM using step gated asymmetric (STAR) cell transistors

Author

Jang, M.W. ; Seo, M.S. ; Kim, Y.T. ; Cha, S.Y. ; Kim, Y.B. ; Kim, S.C. ; Rhee, J.H. ; Cheong, J.T. ; Jung, T.W. ; Pyi, S.-H. ; Kim, H.G. ; Jeong, J.-G. ; Park, S.-K. ; Hong, S.J. ; Park, S.W.

Author_Institution

Div. of R&D, Hynix Semicoductor Inc., Kyounggi-do, South Korea

fYear

2005

fDate

12-16 Sept. 2005

Firstpage

189

Lastpage

192

Abstract

For the first time, we developed successfully the 512Mb DRAMs using step-gated-asymmetric (STAR) cell transistors with 90nm feature size. The STAR with step recessed channel depth of 40nm exhibits distinctly improved electrical characteristics such as BV_DS, junction leakage and word-line capacitance (C_WL), comparing to a conventional planar and recess-channel transistors of the same gate length. The two major merits using the STAR in DRAMs are about 200% improvement of data retention time and low costs of KrF lithography process rather than those of ArF lithography process. Moreover, this STAR technology is able to extend to sub-80nm by scaling STAR depth and width without increasing the concentration of substrate.

Keywords

DRAM chips; field effect memory circuits; lithography; 40 nm; 512 Mbit; 90 nm; DRAM circuit; KrF lithography process; data retention time; improved electrical characteristics; junction leakage; step gated asymmetric cell transistors; step recessed channel depth; word-line capacitance; Boron; Capacitance; Costs; Electric variables; Etching; Lithography; Random access memory; Subthreshold current; Tin; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Device Research Conference, 2005. ESSDERC 2005. Proceedings of 35th European

Print_ISBN

0-7803-9203-5

Type

conf

DOI

10.1109/ESSDER.2005.1546617

Filename

1546617