High-speed electro-optic analogue to digital converters

Author

Mason, R. ; Taylor, J.T.

Author_Institution

Dept. of Electron. & Electr. Eng., Univ. Coll. London, UK

fYear

1993

fDate

3-6 May 1993

Firstpage

1081

Abstract

Interleaved architectures can substantially increase the speed of analogue-to-digital converters (ADCs). Problems of timing jitter have limited the maximum speed of all-electronic ADCs to about 1 Gs/s. An optoelectronic solution is proposed which will remove this restriction and fully exploit the potential of the interleaved architecture. Fully integrated optically triggered sample-and-hold circuits are fabricated for the first time, using GaAs MESFET technology. Preliminary test results are presented

Keywords

III-V semiconductors; MESFET integrated circuits; analogue-digital conversion; gallium arsenide; integrated optoelectronics; sample and hold circuits; A/D convertors; GaAs; MESFET technology; analogue-to-digital converters; electro-optic ADC; high-speed ADC; interleaved architecture; optically triggered S/H circuits; optoelectronic ADC; sample/hold circuits; timing jitter; Analog-digital conversion; Circuit testing; Clocks; Gallium arsenide; High speed optical techniques; Integrated circuit technology; Optical interferometry; Sampling methods; Signal resolution; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on

Conference_Location

Chicago, IL

Print_ISBN

0-7803-1281-3

Type

conf

DOI

10.1109/ISCAS.1993.393922

Filename

393922