• DocumentCode
    2607981
  • Title

    VMOS Electrostatic Protection

  • Author

    Bhatti, I.S. ; Fuller, E. ; Jenne, F.B.

  • Author_Institution
    American Microsystems, Inc., 3800 Homestead Road, Santa Clara, CA 95051. (408) 246-0330
  • fYear
    1978
  • fDate
    28581
  • Firstpage
    140
  • Lastpage
    145
  • Abstract
    Present state of the art MOS devices with 1000 Ã… thick gate oxides have breakdown voltages in the 60-80 volts range. VMOS devices with the same oxide thickness have lower breakdown voltages (25-30 volts) due to higher fields in the oxide at the bottom of the V-groove. A VMOS protection device with higher protection capability than conventional MOS protection devices has been designed and tested. It consists of a poly resistor connected to an nipn diode, followed by an implanted n+ diffusion which acts as a distributed R C network attenuating tihe input voltage spikes. The final section consists of a planar NMOS transistor connected between the n+ diffusion and the VMOS gate. Tests show that this type of protection device is superior to conventional protection devices.
  • Keywords
    Breakdown voltage; Diodes; Electrostatics; Epitaxial layers; MOS devices; MOSFETs; Protection; Resistors; Substrates; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Reliability Physics Symposium, 1978. 16th Annual
  • Conference_Location
    San Diego, CA, USA
  • ISSN
    0735-0791
  • Type

    conf

  • DOI
    10.1109/IRPS.1978.362838
  • Filename
    4208228