DocumentCode
2608199
Title
A high resolution nonlinearity correcting A/D converter architecture
Author
Sculley, T.L. ; Brooke, M.A.
Author_Institution
Sch. of Electr. Eng. & Comput. Sci., Washington State Univ., Pullman, WA, USA
fYear
1993
fDate
3-6 May 1993
Firstpage
1212
Abstract
An architecture is presented for a high resolution analog-to-digital (A/D) converter with tolerance to nonlinearities in the critical timing path as well as offsets and gain errors. An error budget analysis is included. It describes the relationship among the various error sources in the converter
Keywords
analogue-digital conversion; error analysis; error correction; A/D converter architecture; critical timing path; error budget analysis; error sources; gain errors; high resolution; nonlinearity correcting ADC; offset errors; Analog circuits; Calibration; Circuit topology; Computer architecture; Computer science; Error analysis; Error correction; Estimation error; Logic; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
Conference_Location
Chicago, IL
Print_ISBN
0-7803-1281-3
Type
conf
DOI
10.1109/ISCAS.1993.393946
Filename
393946
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