Predicting harmonic distortion in switched-current memory circuits

The major source of distortion in switched current (SI) is identified. It is demonstrated that the distortion in SI circuits is the result of variation in the settling behavior of the current memory cell from one sampling instant to the next. To aid designers of SI circuits, a bound on the total harmonic distortion (THD) is derived in terms of the maximum and minimum settling errors in a current memory cell for a given input signal level. Several examples demonstrate the simplicity of using the formula for the THD bound. The bound in each example is checked against the THD computed from a HSPICE simulation, and by comparing it directly against experimentally observed results. In each case, the actual THD measure is within the proposed bound