DocumentCode :
2608436
Title :
Process integration for thin film passive components
Author :
Collier, Peter ; Hee, Tan Boon ; Zuoqi, Hu
Author_Institution :
Surface Technol. Group, Singapore Inst. of Manuf. Technol., Singapore
fYear :
2003
fDate :
10-12 Dec. 2003
Firstpage :
538
Lastpage :
543
Abstract :
Processes for producing tantalum pentoxide thin film capacitors and tantalum nitride thin film resistors in a combined process flow with multi-level interconnects are demonstrated, as may be applied to wafer level packages or thin film modules. Considerations of materials property and component parameter relations are presented in order to fabricate stable, high tolerance devices. Process capability indices are discussed, based on process measurements and statistical analyses of electrical test results over of a wide range of resistor values. Experimental results are compared to calculations of achievable resistor tolerance distributions taking account of both process losses and particulate contamination. It is shown that a capability model based on fixed etching variations combined with a negative binomial distribution of particulate defects may reproduce the experimental observations and assist in formulating design guidelines.
Keywords :
chip scale packaging; electrolytic capacitors; modules; passivation; photolithography; process capability analysis; tantalum compounds; thin film capacitors; thin film resistors; Ta2O5; TaN; combined process flow; component parameter relations; design guidelines; electrolytic capacitor dielectric; fixed etching variations; high tolerance devices; materials property relations; multilevel interconnects; negative binomial distribution; particulate contamination; passivation layer; photolithography; process capability indices; process integration; process losses; thin film capacitors; thin film modules; thin film passive components; thin film resistors; wafer level packages; Capacitors; Electric variables measurement; Material properties; Packaging; Pollution measurement; Resistors; Statistical analysis; Testing; Transistors; Wafer scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics Packaging Technology, 2003 5th Conference (EPTC 2003)
Print_ISBN :
0-7803-8205-6
Type :
conf
DOI :
10.1109/EPTC.2003.1271580
Filename :
1271580
Link To Document :
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