• DocumentCode
    2608553
  • Title

    Reliability and characterization of dielectric layers used for leaded and lead-free solder application

  • Author

    Lo, Wei-Chung ; Chen, Yu-Chih ; Chen, Yu-Fang ; Fu, Huan-Chun ; Chang, Shu-Ming ; Shen, Li-Cheng ; Hu, Hsu-Tien ; Chen, Kuo-Chuan

  • Author_Institution
    Adv. Process Technol. Dept., Packaging Process Technol. Div., Hsinchu, Taiwan
  • fYear
    2003
  • fDate
    10-12 Dec. 2003
  • Firstpage
    574
  • Lastpage
    577
  • Abstract
    Lots of advanced packaging forms were introduced to meet different application by using the solder balls as the interconnect media between chip and substrate. With the environment protection concerns increasing, lead free solders are playing the more and more important role in this area. The properties and characterization between solder joints and dielectric layers are key reliability issues. The present works mainly focuses on the investigation of the quality of dielectric layers for wafer level chip size packages (WLCSP). In this paper, both the negative tone (Durimide 7510/7320) and positive tone (Durimide 9005) photosensitive materials are evaluated as the dielectric layer for the E-WLCSP. In the E-WLCSP, there were two major bumping processes to be introduced here: Ti/Cu/Ni/Au UBM with 63Sn/Pb eutectic solder and Sn/3.8Ag/0.7Cu lead free solder. The target is to choose the most reliable pairs for positive- and negative-tone polyimides, to meet the different bumping process requirement, and pass the reliability test.
  • Keywords
    chip scale packaging; copper; copper alloys; dielectric thin films; gold; integrated circuit interconnections; integrated circuit reliability; lead alloys; nickel; silver alloys; soldering; tin alloys; titanium; E-WLCSP; Ti-Cu-Ni-Au-SnAgCu; Ti-Cu-Ni-Au-SnPb; UBM; eutectic solder; lead-free solder; leaded solder; negative tone Durimide 7510/7320; negative-tone polyimide; photosensitive materials; positive tone Durimide 9005; positive-tone polyimide; reliability testing; solder ball interconnects; solder joints; wafer level chip size packages; Dielectric materials; Dielectric substrates; Environmentally friendly manufacturing techniques; Gold; Lead; Packaging; Protection; Soldering; Tin; Wafer scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics Packaging Technology, 2003 5th Conference (EPTC 2003)
  • Print_ISBN
    0-7803-8205-6
  • Type

    conf

  • DOI
    10.1109/EPTC.2003.1271586
  • Filename
    1271586